Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a pin capacitor of a semiconductor device, which is coupled to a pad, and a method for fabricating the same.
Semiconductor devices such as a DRAM include a pin capacitor which is positioned in a pad area and coupled between a pad and a ground, in order to reduce noise occurring during power supply and data input/output through the pad.
FIGS. 1A and 1B are diagrams illustrating a pin capacitor of a conventional semiconductor device. FIG. 1A is a plan view of the pin capacitor, and FIG. 1B is a cross-sectional view taken along a line X-X′ in FIG. 1A.
Referring to FIGS. 1A and 1B, the pin capacitor of the conventional semiconductor device includes an isolation layer 12, a gate 17, and a pickup area 14. The isolation layer 12 is formed in a substrate 11 to define a dummy active area 13. The gate 17 is formed on the isolation layer 12 at both sides of the dummy active area 13, and includes a gate electrode 15 and a gate hard mask layer 16 which are sequentially stacked. The pickup area 14 is formed in the substrate 11. At this time, the pin capacitor has a structure in which the substrate 11, the isolation layer 12, and the gate 17 are stacked. The gate 17, the isolation layer 12, and the substrate 11 serve as an upper electrode, a dielectric, and a lower electrode, respectively. The gate 17 is coupled to a pad unit 101, and the pickup area 14 is coupled to a ground unit 102.
In order to increase the integration degree of a semiconductor device, the size of a pad tends to be reduced. Accordingly, the size of the gate 17 of the pin capacitor formed in the pad area is also reduced gradually. As the size of the gate 17 is reduced, the capacitance of the pin capacitor may decrease. Furthermore, as the capacitance of the pin capacitor decreases, the reliability of the semiconductor device may be degraded.